Commit Graph

882 Commits

Author SHA1 Message Date
daniel d35a55ec8e docs: correct the Gamma-W1 track count and table, and name T7 as a Rate prerequisite 2026-08-02 13:52:31 -04:00
daniel 91bd6f51a2 Period detection: silence is not dissent but an absent period is — the agreement denominator is the probes that carried signal 2026-08-02 13:52:31 -04:00
daniel cc4967d21d docs: drop the findings count from T7's open-questions bullet, it drifts as remediation lands 2026-08-02 13:52:31 -04:00
daniel 3e4ba628c3 docs: record Gamma-W1-T7 in PLAN.md, the track that landed without an entry 2026-08-02 13:52:31 -04:00
daniel 048673eb75 Merge Γ-W1-T7: Preserve's splices go pitch-synchronous — the period is detected once at load, over the loop the voice actually plays 2026-08-02 13:52:31 -04:00
daniel e7d7e70201 docs: fix stale Gamma payload-rung numbers in instrument-control-surface (v14/v15 -> v15/v16) 2026-08-02 13:52:31 -04:00
daniel 79189bd316 docs: fix stale v14 limiter rung in shell/instrument/CLAUDE.md to v15 2026-08-02 13:52:31 -04:00
daniel 9228e93750 Preserve's period detection: probes are placed by position, and a sustain loop is the span analysed 2026-08-02 13:50:14 -04:00
daniel 163ab11e05 Handle Psi's ReaperSurface::Count sentinel in decideDropClass — Gamma's exhaustive-switch gate turns it into a hard error on contact
The sentinel is not a surface, so it breaks to the existing unclassifiable-surface refusal rather than joining a real case label.
2026-08-02 13:50:14 -04:00
daniel 334022c0f1 Gamma-W1-T7: gate PSOLA's two untested wires, fix the cadence test's contradictory rationale, add a vacuity guard 2026-08-02 13:50:14 -04:00
daniel 38337229d4 docs: correct Γ's payload rungs to v15/v16/v17 after Ξ took v14
States rung one as spent rather than derivable, so following the instruction
no longer contradicts the stated number — the trap that caused the collision.
2026-08-02 13:50:14 -04:00
daniel 93230208ff Γ-W1-T7: make Preserve's splices pitch-synchronous — the jump is a whole number of the source's own period, detected once at load
30 Hz out-of-band energy 15.45% -> 0.00%; the 29 Hz rate-2.0 detune -133 -> +0 cents.
An unknown period keeps the fixed-window geometry bit for bit. The detector cannot
reach process(): sampler_core does not link it.
2026-08-02 13:50:14 -04:00
daniel f8e57a3cbd Merge Γ-W1-T2: the master bus — limiter, meter publication, and the plugin's first PDC report 2026-08-02 13:50:13 -04:00
daniel 91c1b78d5e Γ-W1-T2: the published GR meter reads the limiter, not the mute
Retire the effectiveGain blend so the meter's minimum tracks smoothGain's own
reduction against real input, unscaled by the transition mute — a toggle over
quiet material now reads no reduction instead of pinning to 0.
2026-08-02 13:50:13 -04:00
daniel 6232851c6b Γ-W1-T2: the limiter toggle is a mute, not a crossfade — the ceiling holds across both transitions
The equal-gain dry/wet blend let a peak through at (1-m) of its level. Now the
fade rides only the limited path and the hard edge lands on silence.
2026-08-02 13:50:13 -04:00
daniel 0612abbddb Γ-W1-T2 review: one restart funnel, tighter ceiling proof, effective-gain meter
Fold setLimiterEnabled's restart request into setInstrumentParams so every writer
keeps the host's latency report in sync. Pin the window-sizing identity, drop the
per-sample modulo, tighten the ceiling tolerance, publish the blended gain.
2026-08-02 13:50:13 -04:00
daniel 3baf4ee50b Γ-W1-T2: the master bus — a true-peak limiter whose ceiling is a theorem, the meter's published half, and the plugin's first PDC report 2026-08-02 13:50:13 -04:00
daniel 4fa021edae Merge Γ-W1-T5: a real Preserve time-stretcher — write rate is duration, tap rate is pitch 2026-08-02 13:47:19 -04:00
daniel 20d86d7900 Merge Γ-W1-T3: staged contour traces draw the curve their exponent defines 2026-08-02 13:47:19 -04:00
daniel abace156a5 Fix inverted splice-cadence test: assert artifact energy, not zero-crossing period
Zero-crossing counting was anti-correlated with the real defect (splice debris
fools it). Now asserts energy outside the fundamental, with an alignable control,
matching test_preserve_low_frequency.cpp's approach.
2026-08-02 13:47:19 -04:00
daniel ab3548dced Merge Γ-W1-T1: one taper, one modifier law, the 10 s stage ceiling 2026-08-02 13:47:19 -04:00
daniel f39fb1b145 Γ-W1-T3: staged contour traces draw the curve their exponent defines
New pure curve_tessellate joins the overlay's node vertices through curveMap,
one sample per pixel column; the knot no longer floats off its own trace.
2026-08-02 13:47:19 -04:00
daniel ac653aa581 Measure Preserve's splice-alignment geometry on low-frequency material
A splice can only relocate by [0.75, 1.25]*window, so periods with no multiple
in that interval never phase-align — at 50 ms, f < 16 Hz and 26.7-32 Hz.
Harness runs by hand; too slow to gate.
2026-08-02 13:47:19 -04:00
daniel 6f39d0137a Merge Γ-W1-T4: the editor floor, the width budget, and the deck row law 2026-08-02 13:47:19 -04:00
daniel a1b42ed1a8 Fix envelope-overlay knot/trace disagreement on odd pixel spans
Generalize curveMidLevel/curveFromMidLevel to curveLevelAt/curveFromLevelAt at
arbitrary phi; knotVtx and its drag inverse now read the phi a knot's truncated
x actually implies, not always 0.5.
2026-08-02 13:47:19 -04:00
daniel ae59e9b70d Γ-W1-T5 remediation: narrow the rate-bound claim, fix baseline/measurement provenance, correct §2.4 framing
Re-derives the splice-cadence inequality and adds a corner probe that FAILS at
P=500 by design, pending a ruling. Names the baseline commit and harness edit,
fixes measurement methodology, corrects the Trigger-AHD/rate coupling framing.
2026-08-02 13:47:19 -04:00
daniel 748aad3538 Merge Γ-W1-T6: exhaustive-switch gate on pure libraries 2026-08-02 13:47:19 -04:00
daniel ee8a956fbd Γ-W1-T1 review fixes: mode-independent taper rounding, sharper drag-step test, reset-sweep verifies stored fields
Swap nearbyint for std::round (MXCSR-independent); derive the finest-drag test
from the editor floor, not the knob; verify resets against fields, not norms;
record the spline-point modifier exclusion.
2026-08-02 13:47:19 -04:00
daniel 589a8e078b Γ-W1-T5: a real Preserve time-stretcher — write rate is duration, tap rate is pitch
Generalizes the correlation-aligned SOLA delay line so the feed and the shift are
independent rates over one ring. Unity is bit-identical to the shipped read, asserted
against a hash baseline captured pre-change.
2026-08-02 13:47:19 -04:00
daniel 3eb72d01c4 One taper, one modifier law: extract param_taper, raise the stage ceiling to 10 s, and make the AHDSR schematic axis the taper itself 2026-08-02 13:47:19 -04:00
daniel ae54ca8128 Re-derive the floor-size test fixtures from the constants and move the ceiling to sample_bands.h 2026-08-02 13:47:18 -04:00
daniel 69e2f1d3e3 Promote switch-exhaustiveness diagnostic to an error on pure libraries (MSVC + GCC/Clang)
MSVC's C4062 is off by default and GCC/Clang's -Wswitch only warns without
-Werror; this repo sets no -Wall/-Werror anywhere. /we4062 and -Werror=switch
now cover both, scoped to pure libraries only.
2026-08-02 13:47:18 -04:00
daniel abb27f08f2 Raise the editor floor to 1190x680, derived from the deck's declared width budget, and make row membership a property of the group 2026-08-02 13:47:18 -04:00
daniel e589addc54 Merge bake diagnosis soundness: every printed claim backed by an observation, write proof only where evidence crosses the plugin boundary 2026-08-02 13:45:38 -04:00
daniel 1c8709e82d Take the read-back back out of the persist; a write verdict belongs only where evidence crosses the plugin boundary
Its false gated six undo points, so an unverified byte-equality assumption could have silently removed Ctrl-Z for a bank mutation that landed.
2026-08-02 13:42:51 -04:00
daniel 25390d5253 Prove every ext-state write by reading the key back, so no guard is constant-true
SetProjExtState's return describes the whole extname. The persist and the instrument's publish now re-read their key; both refusals can finally fire.
2026-08-02 13:14:49 -04:00
daniel 2cb0b52884 docs: correct two false claims in the Phase Ε spec
REAPER's GetUserFileName serves both pickers — the no-save-picker finding was a
regex miss. A new enum value is structural, not additive: BankModel rejects an
out-of-range SourceMode/Tier rather than degrading.
2026-08-02 12:38:41 -04:00
daniel 0afb885987 Make a bake's Banked landing reachable only through the persist upgrade
The dedup path claimed it directly, so a key could be answered Ok pointing at an entry a failed persist never wrote. Write-back is now guarded and three-valued, and landing one request split out of the scan pass.
2026-08-02 12:35:06 -04:00
daniel 1800bd64c3 Prove the bake's answer writes by reading the key back
SetProjExtState's return covers the whole extname, so it never saw one key. The persist verdict now reaches the report, and a throw mid-write no longer claims the landing left nothing behind.
2026-08-02 12:00:34 -04:00
daniel 6cabbd0dd4 Fix the bake scan report's unsound absence-as-signal claim
Gate the summary on any unanswered key and on SetProjExtState's return, print one line per scanned key, and make the undo block stack RAII.
2026-08-02 08:34:59 -04:00
daniel 2f8e88880e Merge bake-answer diagnosis: five named failure modes and a scan report that says what the landing saw 2026-08-02 08:06:45 -04:00
daniel 4abeace925 Merge capture-bounds diagnosis: empirical tolerance, unmeasurable-render refusal, refused renders kept for inspection 2026-08-02 08:06:35 -04:00
daniel 41ca833b86 bake: make the landing scan say what it saw, so a no-answer names its own cause
Splits Ignore into unreadable vs not-a-request and counts every verdict; the report prints only when the pass answered nobody, so its absence proves the action never ran.
2026-08-02 08:00:19 -04:00
daniel 0511d16d4f capture: close batch-quarantine silence, 0-byte asymmetry, and round-two doc overclaims
Batch captures now name the retained-render folder once instead of nothing; Auto/Manual tail modes refuse a 0-byte render like None does; VERIFICATION.md steps 1-3 no longer invite a false conclusion; docs/comments no longer overclaim.
2026-08-02 08:00:12 -04:00
daniel ef0da893b5 docs: add Phase Λ (Linux port) to PLAN.md
Adds the Phase Λ entry: six settled rulings, four open forks, and thirteen tracks across seven waves, from docs/product/linux-readiness.md. Adds the l slug transliteration, and scopes the plan-wide "nothing unanswered" claim, which Λ's open forks break.
2026-08-02 07:52:57 -04:00
daniel c037aa1cb6 docs: rule Phase Rho's three forks
Refuse multi-track; result track always Arrange; follow panel tail. Rho-F2 overrides the mode-following framing: explicit Arrange tags on track and item, plus an explicit-tag-wins filter in detectNewContent.
2026-08-02 07:40:01 -04:00
daniel 734672ba0e docs: scope Phase Λ, the Linux port
Product doc for the extension + ReaSampler 9000 on Linux, downstream of the two Λ-W1 audits: Daniel's six rulings, seven waves, the non-REAPER-host safety contract, and four open forks.
2026-08-02 07:26:55 -04:00
daniel 2005f90c66 capture: state the bounds tolerance as empirical, refuse unmeasurable renders, keep refused ones for diagnosis
The one-frame bound is not provable for a per-edge renderer; the test now shows where it breaks. Refused renders move out of the bank instead of being deleted, so the DAW experiment has something to read.
2026-08-02 07:23:30 -04:00
daniel 61e90af547 docs: record Phase Ε fork rulings in the plan
Ε-F1 proprietary RSBK, Ε-F2 new bank with auto-suffix, Ε-F3 refuse on a
degraded ledger. No Ε track is gated now. Also carries Phase Ρ's plan
sections, authored concurrently in this shared checkout.
2026-08-02 07:06:23 -04:00
daniel 461351ee02 docs: frame Phase Rho — render in place
Product notes for rendering a track's output to a new sibling track at the exact render position, source parked in Design mode, bank never touched. Framed as a third verb (arrange->arrange), not an exception to capture/placement separation. Three open forks.
2026-08-02 07:05:33 -04:00