Commit Graph

7 Commits

Author SHA1 Message Date
daniel f1168e16eb Close Γ-W1-T7 re-review: pitch-sync cadence math, floor-model regression check, evidence-count fix, one-home comments
New cadence-collapse-band test at P=1470 shows PSOLA eliminates the corner rather than regressing it (18.52% -> 0.00%).
2026-08-02 13:52:31 -04:00
daniel 334022c0f1 Gamma-W1-T7: gate PSOLA's two untested wires, fix the cadence test's contradictory rationale, add a vacuity guard 2026-08-02 13:50:14 -04:00
daniel 93230208ff Γ-W1-T7: make Preserve's splices pitch-synchronous — the jump is a whole number of the source's own period, detected once at load
30 Hz out-of-band energy 15.45% -> 0.00%; the 29 Hz rate-2.0 detune -133 -> +0 cents.
An unknown period keeps the fixed-window geometry bit for bit. The detector cannot
reach process(): sampler_core does not link it.
2026-08-02 13:50:14 -04:00
daniel abace156a5 Fix inverted splice-cadence test: assert artifact energy, not zero-crossing period
Zero-crossing counting was anti-correlated with the real defect (splice debris
fools it). Now asserts energy outside the fundamental, with an alignable control,
matching test_preserve_low_frequency.cpp's approach.
2026-08-02 13:47:19 -04:00
daniel ac653aa581 Measure Preserve's splice-alignment geometry on low-frequency material
A splice can only relocate by [0.75, 1.25]*window, so periods with no multiple
in that interval never phase-align — at 50 ms, f < 16 Hz and 26.7-32 Hz.
Harness runs by hand; too slow to gate.
2026-08-02 13:47:19 -04:00
daniel ae59e9b70d Γ-W1-T5 remediation: narrow the rate-bound claim, fix baseline/measurement provenance, correct §2.4 framing
Re-derives the splice-cadence inequality and adds a corner probe that FAILS at
P=500 by design, pending a ruling. Names the baseline commit and harness edit,
fixes measurement methodology, corrects the Trigger-AHD/rate coupling framing.
2026-08-02 13:47:19 -04:00
daniel 589a8e078b Γ-W1-T5: a real Preserve time-stretcher — write rate is duration, tap rate is pitch
Generalizes the correlation-aligned SOLA delay line so the feed and the shift are
independent rates over one ring. Unity is bit-identical to the shipped read, asserted
against a hash baseline captured pre-change.
2026-08-02 13:47:19 -04:00